Same group and same layer design for timing

Same group and same layer design for timing

For the same group of traces in the timing sequence, the same group and the same layer design is generally required, especially the higher-speed bus structure.

Same group and same layer requirements and advantages:

1) All wiring must be on the same layer (the length of the same layer is close), and the wiring is on the same layer. There is no winding on different layers, such as the surface layer.

2) The same group of wires are routed together, and other networks are not allowed to intersect.

3) The same group and the same layer wiring ensures the consistency of the entire wiring environment, that is, the effects of temperature, interference, and medium changes on each wire in the same timing are consistent, and the time delay to the receiving end is even greater. Consistent.

4) If you wind the wires on other layers, it will disrupt the consistency of the entire wiring environment. For example, two of the wires are wound on the surface layer, and the other wires are wound on the inner layer. Since the surface wiring is 100 mils faster than the inner layer per 1000 mils, when the 1000 mil wiring on the surface is the same length as the inner layer, the actual length 100mil electrical delay for layer short circuit. The same length of the surface and inner wiring is actually converted at 1.1:1.

5) The same layer wiring can avoid timing errors caused by inconsistent via lengths.

6) Do not intersperse wires to reduce the impact of crosstalk.

7) At present, we are going to the common signal of the same group of wiring: DDR1/2/3 Data-DQS bus. For PCI, SDRAM, DDR1/2/3 Address/Command/Control signal lines, and high-speed SERDES signals, the same group and the same layer are not required (if it can be better). Other higher-speed buses also have this requirement, depending on the situation.