PCB design and wiring instructions

1. General description

1. Characteristic impedance

 Printed microstrip line (surface layer), Z=65Ω±10%;

 Printed strip line (inner layer), Z=50Ω±10%; differential clock single-ended impedance to ground is 50Ω, differential impedance is 100Ω.

2. Line width recommendation: signal line width=6mil, for some difficult wiring lines 4.5mil, power/ground line width should be 15mil or 30mil depending on the situation.

3. Laminate recommendation: refer to the laminate of the CS1999 reference design, the thickness of the board is 2.4+/-0.2mm, and the number of layers is recommended to not exceed 16-18.

4. BGA chip pin vias: try to keep the lead vias for unused pins except those that affect the wiring.

 2. Power and ground

1. The main types of power supplies are as follows:

 P48V/N48V, 5V (40A), 2V5 (22A), 1V2 (60A), 1V8 (10A), 3V3

(10A) and 5V2N (3A), VDDQ, VTT and VREF; these are digital power supplies

 3V3A, VCCTX_1/2, 1V2A_1/2: These are the analog power output from the linear power module

2. For 5V (40A), 2V5 (22A), 1V2 (60A), 1V8 (10A), 3V3 (10A), the through hole current capability should be considered when the power module output PIN is connected to the power split layer according to the current size. It is recommended Add corresponding filling planes to multiple signal layers around the corresponding PIN, and then use multiple vias to connect the layers to lead current to the corresponding power layer.

3. CS1999, FPGA and optical modules have a variety of analog power supplies. These power supplies are generally linear power supplies or provided after LC filtering. All analog power supplies require power splitting. Suggestion for analog power splitting: split at the signal layer and require upper and lower adjacent The layer must be a signal ground.

 The following is the name of the power supply that needs to be divided:

1) CS1999 analog power supply:

STX0_VDD, STX1_VDD, SRX0_VDD, SRX1_VDD, HTX0_VDD, HTX1_VDD, HRX0_VDD,

HRX1_VDD, SFI5_VDD_DVR, HTX_VDD_DVR.

 2) FPGA

 VCC_PLL_OUT1/2/3, VCCA_3V3_1, 2, VCCTX_1/2, 1V2A_1/2, VCCP_1/2

 3) Optical module: 5V, 3V3, 1V8, 5V2N and other analog power supplies are provided after LC filtering.

4) Others: all power supplies after passing through the inductor L

4. All current vias of inductance 1008PS should be 3A, and the rest should be 1A.

5. Ground plane

 Including signal ground and chassis ground.

 The outer periphery of each layer of signal layer is connected to the corresponding socket.

6. The TAB plane of all LDO power conversion chips (LT1963AEQ, LT1764EQ, LP3883ES) should be defined during wiring and connected to the corresponding plane, the heat dissipation copper area should be increased appropriately, and the back side should also be symmetrically increased with the copper plane (allowed in the layout In this case, the area can be as large as possible), and connect it to the corresponding power layer or ground layer through multiple vias to facilitate heat dissipation. The TAB plane of each chip is defined as follows:

LT1963A/LT1764/LP3883: TAB=GND (ground)

7. For CS1999 power and ground division, please refer to the actual wiring file of its evaluation board.

 Three, decoupling requirements

1. According to the logic diagram design and implementation.

 The decoupling capacitors of each device are evenly placed, small value capacitors are placed as close to the power pin as possible, and large polar capacitors are placed around the chip.

2. Each of the two FPGAs has 5 pin_K7/T7/Y4/AD7/AK7 externally connected to the ground with a 2.00k resistor, and the wiring should be far away from other interference sources. The ground ring can be used to isolate this wiring from other wires.

3. General connection requirements for decoupling capacitors: the wiring of the capacitor pad is as shown below:

Four, signal wiring description

1. General requirements for differential signals:

 The length of the differential line pairs must be strictly matched, and the maximum error is <10mil. All signal lines should be as short as possible except for length requirements

 The differential line pairs should be as close as possible (but to ensure impedance, it is recommended to use 6mil line width 6/9mil spacing), the spacing between other differential pairs is >15mil, and the spacing between other non-differential signal lines>30mil;

 Differential pairs use the same layer to reduce vias and layer change (except for the matching resistors, only the source and destination terminals can be changed through vias).

 When the power plane is divided, the adjacent differential signals of the power plane cannot be routed across the divisions.

 For terminals with matching resistors, the matching resistor connection method is as shown in the figure below, select one for connection, and the wiring length is also as shown in the figure.

 For the series capacitors on the differential line, the capacitors of the differential pair must be placed on the same side (generally required to be placed close to the terminal), and the trace length should match. When the PECL clock adopts AC coupling, the external resistance of the source terminal is connected as follows

 As shown in the figure.

2. Clock signal

 Differential clock

 Including the following signals:

There are three pairs of 622M clock: MSA_RXREFCLK_P/N, MSA_TXREFCLK_P/N, CS1999_REFCLK_P/N.

There are 8 pairs of 156M clock: IF_REFCLK1/2_P/N, XAUI_REFCLK1/2_P/N,

FPGA1/2_CORECLK_P/N, CS1999_IL_REFCLK1/2_P/N.

 See above for these signal routing and matching requirements. The differential clock traces should be as far away as possible from other signal traces, especially parallel traces. Each pair of differential traces is not required to have the same length as other differential pairs, but the maximum length should not exceed 15cm.

 Single-ended LVTTL clock

 Including the following signals: SRAM_CLK, TCAM_CLK

For these signals, the traces should be as short as possible, in principle <3cm, and the longest should not exceed 5cm. For the 25 ohm resistor connected in series, it is required to be as close as possible to the source chip (FPGA) pin.

3. SFI5 interface signal

 This signal is used for high-speed data (3.125G) transmission between the optical module and CS1999, including receiving and sending two groups, the signal is as follows.

1) Try to use the appropriate lowest signal layer to shorten the length of the Stub line; use an arc or 45° bend when the line needs to be turned;

2) Via rules

 All vias remove all pads on the inner layer (only the pads on the wiring layer are kept)

3) It is recommended to refer to the CS1999 reference design wiring file for detailed wiring and via parameters.

4) Do not use the same layer for receiving and transmitting differential pairs

4. Interlaken interface signal

 This signal is used for high-speed data (3.125G) transmission between CS1999 and FPGA. Like SFI5, it includes two groups of receiving and sending. The signals are as follows.

For wiring, see SFI5 signal wiring requirements.

5. XAUI signal

 Used for high-speed signal transmission between FPGA and ZD socket on the backplane.

1) The length of the wire connected to the ZD socket is less than 5" (including the sum of the wiring at both ends of the capacitor in series, and the actual wiring is as good as possible

 Short, in order to reduce the backplane trace length control. It includes the following 8 groups.

LINE0_XAUI_RXDAT_P/N_<3..0> is a set of 4 pairs of 3.125G differential signals;

LINE1_XAUI_RXDAT_P/N_<3..0> is a set of 4 pairs of 3.125G differential signals;

LINE0_XAUI_TXDAT_P/N_<3..0> is a set of 4 pairs of 3.125G differential signals;

LINE1_XAUI_TXDAT_P/N_<3..0> is a set of 4 pairs of 3.125G differential signals;

LINE2_XAUI_RXDAT_P/N_<3..0> is a set of 4 pairs of 3.125G differential signals

LINE3_XAUI_RXDAT_P/N_<3..0> is a set of 4 pairs of 3.125G differential signals;

LINE2_XAUI_TXDAT_P/N_<3..0> is a set of 4 pairs of 3.125G differential signals;

LINE3_XAUI_TXDAT_P/N_<3..0> is a set of 4 pairs of 3.125G differential signals;

2) The error of the equal length of each pair of differential lines is less than 10mil, and each group of 4 pairs does not require strict equal length, but try to reduce the deviation and keep the length as short as possible.

3) For wiring, refer to SFI5 signal wiring requirements.

6. 700M LVDS signal

 Used for high-speed signal transmission between two FPGAs. Including the following four groups:

The receiving and sending differential pairs should not go on the same layer, other cables are generally required to be the same.

7. HSTL signal

The signal connected between U1 (NL3300) and IC2 is an HSTL-1 signal of about 200MHz, please follow the HSTL general wiring requirements.

1) The two-way signal TCAM_DBUS[0:71] and the one-way signal CAM_CLK and TCAM_IBUS must be placed as close to U1 as possible with the 50-ohm terminal matching resistance, and the STUB line length should be as short as possible. It is recommended to follow a trace as shown in the figure below. If the trace is difficult, follow b. Route, match the resistance branch length and the distance between the copy point and U1 Pin as short as possible.

2) The following signal groups are required to have the same length and the error is less than 100mil:

TCAM_CLK, TCAM_CLKO, TCAM_IBUS[7:0], TCAM_DBUS[71:0], TCAM_HITACK,

 TCAM_VALID, TCAM_RDACK

 3) The VTT filter capacitors CP1~CP10 are evenly distributed around the terminal matching resistor.

8. Fast Ethernet signal

1) The following are differential signal pairs, which are the same as general differential signal wiring requirements.

100M_RD+/-, 100M_TD+/-, BACK_100M_TD+/-, BACK_100M_RD+/-, 100M_TX+/-,

100M_RX+/-, RJ_100M_TD+/-, RJ_100M_RD+/-.

2) The following signals are not differential signals, but each group is required to have the same length:

MII_TX_CLK, MII_TXD<3..0>, MII_TXEN is a group, the error is <1cm

 MII_RX_CLK, MII_RXD<3..0>, MII_RXEN, MII_RXER, MII_RX_CRS, MII_RX_COL,

It is a group, the error is <1cm

 9. Side scan signal routing

a) TMS signal routing direction: side scan 2X5 socket FPGA1(IC3)  FPGA2(IC4)

 b) The direction of TCK signal routing is the same as that of TMS.

10. Control bus signal:

 Including LOCAL_AD[31:0], LOCAL_ACK, LOCAL_RW, LOCAL_RDY, LOCAL_STB, LOCAL_ALE

Take a daisy chain connection according to a group of buses.

11. Other data bus signals:

 All other group bus signals that are not mentioned require that the difference between each group of buses should not exceed too much (keep the same order of magnitude), and the length should be as short as possible.

 Five, indicator light description

 The indicators that need to come out of the panel include 3 power and system status indicators, and 3 40G interface status indicators,

The relative position of the indicators on the panel is shown in the figure below.

The corresponding relationship between the panel indicator and the LED on the logic diagram is as follows:

Please place the indicator lights according to the above relative position and corresponding relationship.